The present invention relates generally to a method of testing integrated circuits using a scan-based test, and to an integrated circuit architecture for performing the scan-based testing method.
Integrated circuits designs often incorporate additional logic to support built-in test functions, such as scan-based testing. Such circuits are designed using a “designed-for-test” (DFT) approach which imposes additional design considerations over those which apply to functional design. Such additional considerations may include an assessment of different criteria, such as test performance (such as test coverage), the overhead of adding dedicated test logic, pin-count for test I/O, test application time, and test equipment requirements (for example, in terms of memory for test data and channels). Each criteria is typically evaluated in terms of its impact on fault detection capability, production time and cost of the integrated circuit. For example, reducing test performance may reduce the production time and cost, but may decrease the fault detection capability.
Usually an integrated circuit having an architecture which supports scan based testing is designed to operate in one of two modes, namely, a functional mode and a scan test mode. In functional mode, the various circuit elements of the integrated circuit are interconnected to perform the designed function or utility. On the other hand, in scan test mode the configuration of the circuit elements of the integrated circuits is modified so that memory cells, such as flip-flops, are coupled in a series arrangement as one or more sequences. Each separate series arrangement of memory cells is typically referred to as a “scan chain”.
A typical scan test involves configuring the integrated circuit for scan test mode and “scanning-in” a scan or test vector (that is, a predetermined sequence of zeros and ones) into each scan chain. The test vector is typically generated using Automatic Test Pattern Generator (ATPG) tools. Typically, the number of bits in the test vector will correspond with the number of memory cells in the scan chain.
Having loaded the test vector, the integrated circuit is then configured to operate in functional mode for a predetermined number of clock cycles during which time the memory cells (and other circuit logic) operate on the loaded bits of the test vector. At the end of the predetermined number of clock cycles, each of the memory cells stores a result bit based on the results of the operation.
The integrated circuit is then reconfigured to scan test mode, and the stored result bits are unloaded (or “scanned-out”) into a test analyzer, one bit at a time, from each scan chain synchronous with a clock. The complete sequence of result bits unloaded or output for a scan chain is typically referred to as a “scan-out”. Each scan-out received by the test analyzer is compared with an expected scan-out for a respective test vector to determine whether there are faults in the integrated circuit.
As will be appreciated, as the complexity of integrated circuits increases, the length of the scan chains, and thus the length of the test vectors, also increases. Increasing the length of the test vectors increases the required amount of test data and thus the test storage required for that data. In addition, increasing the length of the test vectors also increases the test application time, which adversely impacts on production times, and thus production cost.
One attempt to reduce the length of the test vectors, and thus the test application time, involves increasing the number of scan chains (in other words, increasing the scan chain count). An example of such an approach is shown in FIG. 1. In the example shown in FIG. 1, different test vectors are loaded into each scan chain (SCAN CHAIN 0, . . . , SCAN CHAIN N) via a respective input (SCAN_IN_0, . . . , SCAN_IN_N) synchronous with a clock signal (SCAN_CLK) and under the control of the scan enable signal (SCAN_EN). After each test vector has been loaded into a respective scan chain the device under test (DUT) is configured to perform a functional operation. The resultant result vectors are then each unloaded via a respective output (SCAN_OUT_0, . . . , SCAN_OUT_N) synchronous with the clock signal.
Although the architecture illustrated in FIG. 1 may be effective at reducing test application time, the architecture does unfortunately require an increased pin count (as compared to a single scan chain implementation), since each scan chain requires a separate respective input and output pin. Thus, the number of scan chains which may be incorporated in the integrated circuit may be limited by the maximum pin-count of the integrated circuit device.
Several methods have been proposed to increase the scan chain count without unduly increasing the pin-count.
One conventional method involves grouping scan chains into “sets” comprising plural scan chains. Each set shares a common input pin and a common output pin and receives the same test vector. In some methods, the pin-count may be further reduced by compressing the test vector prior to scanning the test vector into a respective scan chain so as to thereby reduce the length of the data stream input into the device under test, and thus reduce the test data volume test and test data memory storage requirements. For example, the test vector may be compressed using a code-based compression scheme in which test codes contained in the test vector are compressed into code words, and an on-die built-in decoder module, such as a decoder circuit, decompresses the compressed test vector to recover the test codes.
Hamazaoglu et al. (1999) outlines an architecture, referred to as the Illonois Scan Architecture (ISA), which attempts to reduce test data volume and test application time by dividing a scan chain into multiple segments. FIG. 2 depicts an example of an conventional ISA architecture which includes scan chain sets (SET ‘A’, . . . , SET ‘N’). Each scan chain in a set receives a test vector derived from a test input received at a respective scan input (SCAN_IN_0, . . . , SCAN_IN_N). In this example, each test input is a data stream which has been compressed using a suitable coding scheme, and which is decompressed by decompression logic to provide the test vector to the respective scan chain set.
The architecture illustrated in FIG. 2 decreases the number of test vectors required to maintain similar scan coverage to a standard linear scan of the type described above. However, although this architecture may reduce the test application time and pin count as compared to a standard linear scan (and particularly when compared to a full linear scan), the resultant pin-count, and thus the required ATPG tester channels, is still nevertheless dependent upon the number of scan chain sets. Moreover, scan compression involving a single scan input/output pair requires highly complex compression and decompression circuitry, resulting in packages with questionable test coverage.
There is a need for an improved scan architecture and method which reduces the volume of test data and minimizes pin-count, whilst maintaining effective test coverage.